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IS43R32400D - 128Mb DDR SDRAM

General Description

for x32 A0-A11 A0-A7 BA0, BA1 DQ0 DQ31 CK, CK CKE CS CAS RAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Column Address Strobe Command Row Address Strobe Command WE DM0-DM3 DQS0-UDQS VDD VDDQ VREF VSS VSSQ NC Write En

Key Features

  • Double-data rate architecture; two data transfers per clock cycle.
  • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver.
  • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs.
  • Differential clock inputs (CK and CK).
  • DLL aligns DQ and DQS transitions with CK transitions.
  • Commands entered on each positive CK edge; data and data mask referenced to both e.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS43R32400A 4Meg x 32 128-MBIT DDR SDRAM
IS43R32400E 128Mb DDR SDRAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS43R32400D 4Mx32 128Mb DDR SDRAM SEPTEMBER 2011 FEATURES • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs • Differential clock inputs (CK and CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation • Data Mask for write data. DM masks write data at both rising and falling edges of data strobe • Burst Length: 2, 4 and 8 • Burst Type: Sequential and Interleave mode • Programmable CAS latency: 2, 2.