IS43R32400D Datasheet PDF - Integrated Silicon Solution 128Mb DDR SDRAM Specs

IS43R32400D - 128Mb DDR SDRAM

Datasheet Summary

Description

for x32 A0-A11 A0-A7 BA0, BA1 DQ0 DQ31 CK, CK CKE CS CAS RAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Column Address Strobe Command Row Address Strobe Command WE DM0-DM3 DQS0-UDQS VDD VDDQ VREF VSS VSSQ NC Write En

Features

Double-data rate architecture; two data transfers per clock cycle.
Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver.
DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs.
Differential clock inputs (CK and CK).
DLL aligns DQ and DQS transitions with CK transitions.
Commands entered on each positive CK edge; data and data mask referenced to both e.

Datasheet Details

Part number	IS43R32400D
Manufacturer	Integrated Silicon Solution
File Size	1.45 MB
Description	128Mb DDR SDRAM
Datasheet	IS43R32400D Datasheet
Additional preview pages of the IS43R32400D datasheet.

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Full PDF Text Transcription

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IS43R32400D 4Mx32 128Mb DDR SDRAM SEPTEMBER 2011 FEATURES • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs • Differential clock inputs (CK and CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation • Data Mask for write data. DM masks write data at both rising and falling edges of data strobe • Burst Length: 2, 4 and 8 • Burst Type: Sequential and Interleave mode • Programmable CAS latency: 2, 2.

Published: Jul 25, 2016 |